ECE 2300 (Digital Logic design)

Midterm 1

25%

Midterm 2

25%

Final

35%

Quizzes*/Assignments

15%

Total

100%

Week#

Topics

1

Number Systems

2

Boolean Algebra

3

Simplification of Boolean Functions using Boolean identities.

4

Simplification of Boolean Functions using K-maps.

5 ,6

Analysis and design of combinational logic circuit/Midterm- I

7-10

Multi-input Output Combinational circuits, Design of binary adders, comparators, decoders, encoders, multiplexers, and demultiplexers. Circuits such as decoders, multiplexers, and binary adders. / Midterm II

11-13

Latches and Flip-flops, Analysis and design of synchronous sequential circuits.

14, 15

Design of Registers and Counters.
Verilog description of typical Synchronous sequential circuits such as counters and registers.
-- Review.

16 Final Exam

 

Text: "Digital Logic with an introduction to Verilog and FPGA-based design" by M. Rafiquzzaman and S. McNinch, Wiley, ISBN# 9781119621546, First edition, August 2019